Cadence Design announces ongoing collaboration with Samsung Foundry

Cadence Design Systems announced a broad collaboration with Samsung Foundry that includes technology advancements to accelerate design for AI and 3D-IC semiconductors, including on Samsung Foundry’s most advanced gate-all-around nodes. The ongoing collaboration between Cadence and Samsung significantly advances system and semiconductor development for the industry’s most demanding applications, including AI, automotive, aerospace, hyperscale computing and mobile. Through this close collaboration, Cadence and Samsung have demonstrated the following: Cadence.AI enables lower leakage power and development of SF2 GAA test chips: Cadence, in close collaboration with Samsung Foundry, has leveraged the Cadence Cerebrus Intelligent Chip Explorer and its AI technology in both DTCO and implementation to minimize leakage power on their SF2 GAA platform. Compared to the best-performing baseline flow, the Cadence.AI result achieved a more than 10% reduction in leakage power. As part of this ongoing collaboration, a mutual customer is actively involved in the development of a test chip using Cadence.AI for an SF2 design. Cadence backside implementation flow certified for Samsung Foundry SF2: As a result of extensive collaboration between Cadence and Samsung Foundry, a complete Cadence backside implementation flow has been certified for the SF2 node to accelerate the development of advanced designs. The full Cadence RTL-to-GDS flow, including the Genus Synthesis Solution, Innovus Implementation System, Quantus Extraction Solution, Pegasus Verification System, Voltus IC Power Integrity Solution and Tempus Timing Signoff Solution has been enhanced to support backside implementation requirements such as backside routing, nano TSV insertion, placement and optimization, signoff parasitic extraction, timing and IR analysis, and DRC. The Cadence backside implementation flow has been validated with a successful Samsung SF2 test chip, demonstrating the flow is ready for use. Cadence has collaborated with Samsung Foundry to enable solutions for Samsung Foundry’s multi-die offerings: The Cadence Integrity 3D-IC platform is enabled for all of Samsung’s multi-die integration offerings, and its early analysis and package awareness features are now compliant with Samsung’s 3DCODE 2.0 version. In addition, Cadence and Samsung have expanded the multi-die collaboration by enabling differentiating technologies like thermal warpage analysis using the Cadence Celsius Studio and system-level LVS with Cadence Pegasus Verification System. Cadence is also supporting Samsung with a package PDK that reduces design time with the Allegro X system. Combined with the Integrity 3D-IC platform, it optimizes the package design flow. Cadence.AI’s Virtuoso Studio flow successfully deployed for analog circuit process migration: Purpose-based instance mapping in the AI-powered Virtuoso Studio provided rapid retargeting of the schematics, while circuit optimization in Virtuoso Studio’s Advanced Optimization Platform helped Samsung achieve a 10X improvement in turnaround time when migrating a 100MHz oscillator design from 14nm to 8nm. In addition, a FinFET-to-GAA analog design migration reference flow is available for joint customers, with successful experimental results.