Arteris IP launches Arteris FlexNoC 5 physically aware network-on-chip IP

Arteris announced the launch of Arteris FlexNoC 5 physically aware network-on-chip interconnect IP. FlexNoC 5 enables SoC architecture teams, logic designers and integrators to incorporate physical constraint management across power, performance and area to deliver a physically aware IP connecting the SoC. This technology enables 5X faster physical convergence over manual refinements with fewer iterations from the layout team for automotive, communications, consumer electronics, enterprise computing, and industrial applications. Manual workflows typically include numerous iterations of pipeline insertions, effort-intensive creation of constraints for physical placement of units, and lengthy NoC placement plus route iterations to converge on the SoC PPA targets. By contrast, FlexNoC 5 physical awareness eliminates these iterations and shortens the duration of various manual steps, facilitating up to 5X faster physical convergence of the back-end physical design time and effort. The resulting physically optimized NoC IP instance is then ready for output to physical synthesis and place and route for implementation.